FIG. 1 shows a frequency-providing circuit 10, as known in the art, which is typically employed in instruments such as pulse or pattern generators. The frequency-providing circuit 10 comprises an oscillator 20 with a certain frequency range f.sub.min to f.sub.max, an output thereof being coupled via a line 25 to a frequency divider circuit 30. The frequency divider circuit 30 is used to divide an output frequency f.sub.osc of the oscillator 20 on line 25 to an output frequency f.sub.out &lt;f.sub.min. For setting the output frequency f.sub.out, the oscillator 20 receives an oscillator control signal on a line 40 and the frequency divider circuit 30 receives a divider control signal on a line 50.
The range of the output frequency f.sub.out can be provided in several sub-ranges in accordance with a selected divide factor DF provided by the divider control signal on line 50 to the frequency divider circuit 30. In case that the frequency range of the oscillator 20 is e.g. f.sub.min :f.sub.max =1:2 with f.sub.max =100 MHz, the range of the output frequency f.sub.out can be provided in several sub-ranges as depicted in the below table:
DF f.sub.out Sub-range 1 1 50.00 . . . 100.0 MHz Sub-range 2 2 25.00 . . . 50.00 MHZ Sub-range 3 3 12.50 . . . 25.00 MHz Sub-range n n 50/2.sup.n . . . 100/2.sup.n MHz
When the output frequency f.sub.out is to be changed, the oscillator 20 receives a specified oscillator control signal 40 and the frequency divider circuit 30 a specified divider factor DF on line 50.
FIGS. 2a and 2b show examples wherein the output frequency f.sub.out is to be changed. In FIG. 2a, the output frequency f.sub.out is to be changed from a frequency f.sub.old to a new frequency f.sub.new, whereby the two frequencies f.sub.old and f.sub.new are within one sub-range. The oscillator 20 sweeps between corresponding oscillator frequencies f.sub.osc--old to f.sub.osc--new within a certain settling time, usually in the range of microseconds up to milliseconds. During that settling time, the output frequency f.sub.out changes continuously from f.sub.old to f.sub.new and is always somewhere between f.sub.old and f.sub.new.
In FIG. 2b, the two output-frequencies f.sub.old and f.sub.new are in different sub-ranges. The oscillator 20 has to be programmed to a new frequency and the frequency divider circuit 30 has to change the divide ratio. Changing the divider factor DF can happen from one clock period to another while changing the oscillator frequency f.sub.osc takes some more time (cf. FIG. 2A). That means that, at the beginning of a change in the output frequency f.sub.out, the oscillator frequency still remains at the value f.sub.osc--old while the divider factor DF has been changed from an old divider factor DF.sub.old to a new divider factor DF.sub.new. Thus, the output frequency f.sub.out is immediately changed from a value f.sub.out =f.sub.osc--old /DF.sub.old to a value f.sub.out '=f.sub.osc--old /DF.sub.new, whereby the value f.sub.out ' can exceed the range between the two output-frequencies f.sub.old and f.sub.new. In FIG. 2b, the output frequency f.sub.out is first changed between two sub-ranges from f.sub.old to f.sub.new and then back to f.sub.old. In contrast to FIG. 2a, the output frequency f.sub.out exceeds the range between f.sub.old and f.sub.new during the respective settling time of the oscillator 20.
As well in the case of FIG. 2a as in case of FIG. 2b it is impossible to provide a new output frequency f.sub.out without getting `wrong` frequencies during the settling time of the oscillator 20. This in particular undesirable when testing the dynamic behavior of circuits like Phase Locked Loops (PLLS) or clock recovery circuits.
A more severe problem, however, occurs in the case of FIG. 2b wherein the output frequency f.sub.out exceeds the frequency range between f.sub.old and f.sub.new during the settling time. This is in particular unacceptable, for example, when a user wants to check an upper operating limit of a circuit, since the frequency change can lead to a much higher frequency than desired. The test circuit can thus produce failures during the settling time or can get out of lock.